Research Activities

  • 2008 - now, in charge of coordinating ISEP Research activities, Head of LISITE laboratory (3 teams, 18 permanent researchers, currently 19 PhD students)
  • 1996 - Now:  Heading a team involved in Low Power Design Techniques, Ultra Low Voltage Design with advanced technologies (SOI Partially and Fully Depleted, Multi-Gates FD-SOI, NV-Resitive RAM etc…) and Design-Technology Interaction. Partnership with major companies in France: CEA/LETI, STMicroelectronics, ATMEL, Thales, SORIN group…
  • 1999: Spent 6 months sabbatical at Stanford University where I joined Professor Giovanni De Micheli’s group.
  • 1993-1996: Head of GaAs design team within LIP6-UPMC working on the design of cell libraries and a set of tools for High Speed GaAs circuit design. As a demonstrator a RISC microprocessor was implemented using VITESSE technology and our libraries, design methodology and tools.
  • 1989-1993: As a part of an ESPRIT project, developed a design methodology for the procedural generation and characterization of optimized VLSI sub-blocks such as RAM, ROM, Multipliers... in Bulk technology.
  • 1988: Joined IBM research and development laboratory at Corbeil-Essonnes where I was involved in SRAM memory design with advanced CMOS Bulk technologies.
  • 1985-1989: As a par of my Ph. D. research, I worked on compilation and characterization of cells for VLSI design. I proposed an approach for the synthesis of complex combinatory cells based on a set of logic synthesis tools, generation and characterization of final layout masks.  The second part of the thesis dealt with SRAM memory compilers.

PhD Students Advisor - Review Committees

  • Participated to more than 20 PhD thesis Review Committees in France and abroad.
  • Advised 15 PhD students, all successfully completed.
  • Currently advisor or co-advisor of 7 PhD students.

Expert For Research Institutions

  • Expert for the Swiss Science Foundation, Switzerland,
  • Expert for the AII (Industrial Innovation Agency) French Research Funding Agency for Industry, now merged with OSEO,
  • Expert for ANR (National Research Agency),
  • Expert for the OMNT (Micro Nano Technology Observatory),
  • Member of the jury of the “Paris Innovation Award” in 2005,

Involvement in Conferences and Journals

  • General Chair of ISCAS 2010 held in Paris
  • Founder and General Chair of the FTFC (Low Voltage and Low Power) Workshop in 1997, the workshop is held in Paris every two years. Starting from 2008 FTFC has been held respectively in Belgium, Switzerland, Quebec and then Morocco. FTFC is now a CAS Technically co-sponsored Conference.
  • Involvement in numerous Technical and Program Committees of IEEE conferences (ISCAS, DAC, NEWCAS, DATE, ICECS, DELTA, VLSI-SoC, ICICDT)
  • Tutorial Chair at IEEE NEWCAS 2006
  • Special Sessions Chair at IEEE ICECS 2007, IEEE NEWCAS 2011
  • Track Chair, VLSI-SoC 2006
  • Panel organizer and moderator at IEEE NEWCAS 2005, ICICDT 2007
  • Panel organizer and moderator at SAME 2006, Sophia Antipolis, Nice 2006
  • Short course on VHDL Modeling for Low Power at Marlow workshop in 2004
  • Local arrangement chair of DATE in 2004
  • International Liaison in IEEE ICECS 2006, IEEE NEWCAS, MWCAS 2007, IEEE ISCAS 2007, 2009, 2011, IEEE DELTA 2008, 2009, 2010, 2011,
  • Session Chair in many conferences (DATE, NEWCAS, ICICDT, VLSI-SOC…)
  • Conference Chair of ICICDT 2008 held in Grenoble, Minatec
  • Local arrangement chair of IEEE HISTELCON (supported by IEEE region 8) in September 2008
  • Reviewer for IEEE journal "Transaction on Computer Aided Design", the Elsevier journal “Microelectronics Journal”, UK
  • Member of the “Microelectronics Journal” Board of Editors, Elsevier, UK
  • Guest editor of a special issue on "SOC for Telecommunication”, “Annales des Télécommunications”, 2004
  • Representing ISEP and co-founder of GIS eSys (Paris Research Network in Electronics),

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