Main Technical Achievments

Skills

Management

  • Education Management,
  • Research Management,
  • International Cooperation Management, Research and Education,

Research

  • Device and Circuit Interaction for Advanced Technologies (PD-SOI, FD-SOI, TFET, Molecular),
  • Low Power and Low Voltage Digital Circuit Design,
  • Low Power and Low Voltage SRAM Memory Circuits Design,
  • Low Power Non Volatile Memories (OxRAM, CBRAM),
  • Implantable Biomedical Devices.

 

 

Due to the need for more interaction between device and circuits in advanced technology nodes, Pr. Amara started research activities in advanced technologies assessment from the low voltage and low power perspective a decade ago. Before that he was mostly involved in Low Voltage and Low Power design techniques at circuit and architectural level. His most recent influential contribution is in developing low-voltage and low power Silicon On Insulator (SOI) and Tunneling Field Effect Transistors (TFET) circuits and their design methodologies. He has made high impact contributions to academia and industry with more than 120 publications and talks, including 24 invited talks and tutorials, at IEEE-related conferences and workshops and at universities and industries. He aIso holds two significant patents [1,4], and has coauthored/edited 3 books and 3 book chapters. He is a recipient of five awards, his students are recipients of 6 awards. A summary of his recent achievements follows.

  1. Low-Voltage and Low Power Circuits with SOI-based technologies:

Since as early as 1997 (at this date, he Launched FTFC a low voltage and low power workshop that is now a technically CASS co-sponsored conference), Dr. Amara has led SOI low-voltage high-density SRAM circuit design, as evinced by 30 successive presentations at IEEE-related conferences excluding 2 tutorials, one keynote and 7 invited talks in addition to 2 journal papers, one book, one book chapter and two patents. He also advised 6 PhD students in this topic. The design is focused on sub-threshold operation with advanced technologies with emphasis on speed, stability, robustness against process variations and low power consumption. In particular he pioneered (Silicon-On-Insulator) SRAM designs with both Partially and Fully Depleted devices (PD-SOI, FD-SOI). His Four-Transistor Self-Refresh PD-SOI SRAM cell using the first dynamic Vth (threshold voltage) achieved low-voltage operation as low as 0.4 V with a high stability and reduced cel lsize.  This work was awarded the 2003-2004 Intellectual Property Award. A systematic design methodology dedicated to partially depleted SOI (PD-SOI) SRAM memory cells has been proposed.
His work on Double-Gate FD-SOI led to the proposition of a Single-ended sub-32 nm Asymmetrical Four-Transistor Double-Gate FD-SOI SRAM cell that combines a high stability with low-voltage operation and high speed and innovative current and voltage sense amplifiers.
His high interest in SOI technology led him to work on further optimization of this technology for low power applications. In a collaborative project with CEA LETI and STMicroelectronics, he worked on circuit design with a new FD-SOI device with an Ultra -Thin body and Ultra-Thin Buried-Oxide (UTBB-FDSOI). This is a simple and revolutionary way to obtain a multiple-Vth FD-SOI technology that bridges the gap between existing Bulk MOS and beyond 20nm technology nodes. New SRAM circuit architectures based on this device have been proposed. This new technology is now adopted as a mainstream by STMicroelectronics and IBM as announced in 2012 and by Global Foundries on February 2013. Pr. Amara was among the first researchers in France to believe on the benefits of this technology and to promote it for low voltage and low power portable/wearable/implantable devices.

  1. Low-Voltage and Low Power Circuits with T-FET based technology:

In parallel, the team he is leading has proposed a new SOI Tunneling-FET (TFET) device. This is a new device that is under investigation for ultra low leakage and medium performance applications. This proposed device architecture achieved an ultra-low leakage current and more than 3 times higher Ion current than state-of-the-art TFET devices. This achievement is an outstanding contribution to solve the problem of the low Ion current of the TFET and opens new avenues to innovative designs in ultra-low power medium-speed applications.  Innovative Ultra-Low leakage SRAMs circuits and architectures have been published. This research activity is gaining more and more interest from the semiconductor companies and research laboratories.


     
E-mail : amara.amara@isep.fr