Publications - Tutorials - Keynotes - Panels - Invited Lectures

Publications, Tutorials, Lectures, Keynotes, Panels

Books

  1. A. Amara, T. Ea, M. Belleville, "Emerging Technologies & Circuits", Springer 2010
  2. A. Amara, O. Rozeau (co-editors), "Doube-gate Devices: Technology & Design", Springer 2008
  3. A. Jalabert, A. Amara, F. Clermidy, "Molecular Electronics: Material, Devices and Applications", Springer 2008

Chapters in books

  1. C. Anghel, A. Amara ; Beyond conventional CMOS technology: Challenges for new design concepts - Springer 2011
  2. B.Giraud, O. Thomas, A. Amara, A. Vladimirescu, M. Belleville SRAM Circuit Design With Double-Gate Devices: Technology and Design - Springer 2008
  3. A. Amara, P. Royannez VHDL for Low-Power Electronics Design CRC Press, USA 2004

Patents

  1. Bastien Giraud, Amara Amara, "Single Ended Asymmetric 4T Double Gate Memory Cell", Patent N° EN 07 03955, 2007
  2. Amara AMARA, Olivier Thomas, "Self-Refresh Partially Depleted SOI SRAM memory cell", Patent N° 03 04127, April 2nd 2003

Journals

  1. Jean-Philippe Noel, Olivier Thomas, Marie-Anne Jaud, Olivier Weber, Thierry Poiroux, Claire Fenouillet-Beranger, Pierrette Rivallin, Pascal Scheiblin, François Andrieu, Maud Vinet, Olivier Rozeau, Frederic Boeuf, Olivier Faynot and Amara Amara,"Multi-VT UTBB FDSOI Device Architectures for Low Power CMOS Circuit", IEEE Transactions on Electron Devices, 2011
  2. Costin Anghel, hraziia hraziia, anju Gupta, Amara Amara, Andrei Vladimirescu, 30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current, in IEEE Transaction on Electron Devices, IEEE, 2011.
  3. C. Anghel, P. Chilagani, A. Amara, and A. Vladimirescu, ‘‘Tunnel Field Effect Transistor with Increased ON Current, Low-k Spacer and High-k Dielectric’’,Applied Physics Letters, Vol. 96, pp. 122104, 2010.
  4. M. Ichihashi, H. Lhermet, E. Beign´e F. Rothan, M. Belleville and A. Amara, “An On-Chip Multi-Mode Buck DC-DC Converter for Fine- Grain DVS on a Multi-Power Domain SoC using a 65-nm Standard CMOS Logic Process,” JOLPE (Journal of Low Power Electronics), Vol.6, Number 1, April 2010
  5. A Valentian, O. Thomas, A. Vladimirescu, A. Amara Modeling Subthreshold SOI Logic for Static Timing Analysis T-VLSI Jun. 200
  6. B. Giraud, A. Amara Advanced Analysis of 6T SRAM Cells in Double-Gate CMOS J. of Physics Jan. 2008
  7. A. Amara, F. Amiel, T. Ea FPGA vs. ASIC for low power applications Microelec. J. Jul. 2006 Vol. 37, No.8, pp. 669-677 Elsevier Ltd
  8. P. Royannez , A. Amara A CMOS/GaAs DCFL comparative survey based upon designed multiplier generators J. of Elec. Engg. 1998 No. 3-4, pp. 76-80

 

IEEE and IEEE-sponsored Conferences - Period 2005-2012

Year 2012

  1. hraziia hraziia, Andrei Vladimirescu, Amara Amara, Costin Anghel, An analysis on the ambipolar current in Si double-gate tunnel FETs, in Solid-State Electronics, Elsevier, 2012.
  2. hraziia hraziia, Costin Anghel, Andrei Vladimirescu, Amara Amara, Jean-Michel Portal, Marc Bocquet, Christophe Muller, Damien Deleruyelle, Santhosh Onkaraiah, Marina Reyboz, Olivier Thomas, Bipolar OxRRAM-based non-volatile 8T2R SRAM for information back-up, in EuroSOI, 2012.
  3. Adam Makosiej, Rutwick Kumar, Andrei Vladimirescu, Amara Amara, Costin Anghel, A 32nm Tunnel FET SRAM for Ultra Low Leakage, in ISCAS 2012, IEEE, 2012.
  4. Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara, Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization, in DATE, 2012.

Year 2011

  1. Adam Makosiej, Andrei Vladimirescu, Olivier Thomas, Amara Amara, ULP Variability-Insensitive SRAM Design in sub-32nm UTBB FDSOI CMOS, in EuroSOI 2011, 2011.
  2. Costin Anghel, Andrei Vladimirescu, Amara Amara, Design of Silicon Double Gate Tunnel FETs with Ultra Low Ambipolar Currents, in EUROSOI 2011, IEEE, 2011.
  3. Ashutosh Ghildiyal, Balwant Godara, Karima Amara, Renzo Dal, Amara Amara, Ultra Wideband for in and on-body medical implants: A study of the Limits and new opportunities, in European Conference on Antennas and Propagation 2011 EUCAP-2011, EurAAP, 2011.
  4. Ashutosh Ghildiyal, Balwant Godara, Amara Amara, Wakeup transmitters for emergency situations in medical implants: a UWB solution, in IEEE International Conference on Ultra Wideband, 2011.
  5. Khaja Shaik, Amara Amara, Chetan D.Parikh, Arjun Singhal, Low power and fast adder implementation with Double Gate MOSFETs, in Faible Tension Faible Consommation (FTFC), IEEE, 2011.
  6. Chetan D.Parikh, Dipankar Nagchoudhuri, Amara Amara, A 0.7-V Rail-to-Rail Buffer Amplifier with Double-Gate MOSFETs, in Faible Tension Faible Consommation (FTFC), IEEE, 2011.
  7. Ashutosh Ghildiyal, Balwant Godara, Amara Amara, An ultra-low power MAC protocol for in-body medical implant networks, in 2nd International ICST Conference on Wireless Mobile Communication and Healthcare Mobihealth 2011, ICST, 2011.
  8. Ashutosh Ghildiyal, Balwant Godara, Amara Amara, Design of an ultra low power MAC for a heterogeneous in-body sensor network, in The 6th International ICST Conference on Body Area Networks BodyNets 2011, ICST / IEEE, 2011.
  9. Ashutosh Ghildiyal, Balwant Godara, Amara Amara, Optimised beaconing for TDMA based heterogeneous body sensor network MAC, in International Conference on Wireless and Mobile Networks (ICWMCN), AgoraPlace, 2011.
  10. Islam Seoudi, Karima Amara, Fabrice Gayral, Renzo DalMolin, Amara Amara, Multi-electrode system for pacemaker applications, in ICECS 2011 International Conference on Electronics, Circuits, and Systems, IEEE, 2011.

Year 2010

  1. UWB for in-body medical implants : A viable option, (ICUWB), 2010 IEEE International Conference on Ultra-Wadeband,1 Nov 2010, Ghildiyal, A.; Amara, K.; Molin, R.D.; Godara, B.; Amara, A.; Shevgaonkar, R.K.;
  2. 32nm and Beyond Multi-Vt Ultra-Thin Body and BOX FDSOI : From device to circuit, Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 3 Aug 2010, Thomas, O.; Noel, J.-P.; Fenouillet-Beranger, C.; Jaud, M.-A.; Dura, J.; Perreau, P.; Boeuf, F.; Andrieu, F.; Delprat, D.; Boedt, F.; Bourdelle, K.; Nguyen, B.-Y.; Vladimirescu, A.; Amara,A.;
  3. Pulse width degradation in 45nm ASIC design due to global and environmental variations, International Conference on Microelectronics (ICM), 2009, Chawla, T.; Marchal, S.; Amara, A.; Vladimirescu, A.;
  4. An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology, Fifth IEEE International Symposium on Electronic Design, Test and Application, 2010. DELTA '10’, Giraud, B.; Amara, A.; Thomas, O.;
  5. “UT2B-FDSOI Device Architecture Dedicated to Low Power Design Techniques”, J.-P. Noel, O. Thomas, M.-A. Jaud, C. Fenouillet-Beranger, P. Rivallin, P. Scheiblin, T. Poiroux, F. Boeuf, F. Andrieu, O. Weber, O. Faynot and A. Amara, ESSDERC 2010, pp. 210-213
  6. “32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From Device to Circuit”, O. Thomas, J.-P. Noel, C. Fenouillet-Beranger, M.-A. Jaud, J. Dura, P. Perreau, F. Boeuf, F. Andrieu, D. Delprat, F. Boedt, K. Bourdelle, B.-Y. Nguyen, A. Vladimirescu and A. Amara, ISCAS 2010, pp. 1703-1706
  7. UWB for in-body medical implants : A viable option, (ICUWB), 2010 IEEE International Conference on Ultra-Wadeband,1 Nov 2010, Ghildiyal, A.; Amara, K.; Molin, R.D.; Godara, B.; Amara, A.; Shevgaonkar, R.K.;

Year 2009

  1. Advances in 3D CMOS Sequential Integration , P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Previtali, C. Tabone, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli, F. Allain, V. Mazzocchi, D. Lafond, O. Thomas, O. Cueto, N. Bouzaida, D.Fleury2, A. Amara1, S. Deleonibus and O. Faynot, IEEE IEDM 2009, San Francisco, USA
  2. M. Ichihashi, H. Lhermet, E. Beigne, F. Rothan, M. Belleville and A. Amara, “A 65-nm On-Chip Multi-mode Asynchronous Local Power Supply Unit for Multi-Power Domain SoCs Achieving Fine Grain DVS,” A-SSCC (IEEE Asian Solid-State Circuit Conference), pp.93– 96, November 2009
  3. M. Ichihashi, H. Lhermet, E. Beign´e, F. Rothan, M. Belleville and A. Amara, “On-Chip DC-DC Converter for IP-Level Dynamic Voltage Scaling,” NEWCAS-TAISA (IEEE International Northeast Workshop on Circuits and Systems), June 2009
  4. M. Ichihashi, “Design Requirement of On-Chip DC-DC Converter for Block-Level Dynamic Voltage Scaling,” PRIME (IEEE International Conference on Ph.D. Research in Microelectronics and Electronics), pp.64–67, July 2009
  5. M. Ichihashi, H. Lhermet, E. Beign´e, F. Rothan, M. Belleville and A. Amara, “An On-Chip Multi-Mode Buck DC-DC Converter for Fine- Grain DVS on a Multi-Power Domain SoC using a 65-nm Standard, CMOS Logic Process,” PATMOS (Power and Timing Modeling, Optimization and Simulation), September 2009
  6. P. Nasalski, A. Makosiej, B. Giraud, A. Vladimirescu and A. Amara, SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch, Proc. ISCAS09, Taipei, Taiwan.
  7. T. Chawla, S. Marchal, A. Amara and A. Vladimirescu, Pulse-Width-Variation-Tolerant Clock Tree Using Unbalanced Cells for Low Power Design, Proc. MWSCAS 2009, Cancun, Mexico
  8. J-P Noel, O. Thomas, C. Fenouillet-Beranger, M-A Jaud, A. Amara; "Robust Multi-VT 4T SRAM Cell in 45nm Thin BOx Fully-Depleted SOI Technology with Ground Plane"; ICICDT, Austin, Texas, Etats-Unis, Mai 2009
  9. J-P Noel, O. Thomas, C. Fenouillet-Beranger, M-A Jaud, P. Scheiblin, A. Amara; "A Simple and Efficient Concept for Setting up Multi-VT Devices in Thin BOx Fully-Depleted SOI Technology", ESSDERC, Athènes, Grèce, September 2009
  10. Impact of intra-die random variations on clock tree, NORCHIP, 2009, Chawla, T.; Marchal, S.; Amara, A.; Vladimirescu, A.;
  11. Local Mismatch in 45nm digital clock networks, Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC '09, Chawla, T.; Marchal, S.; Amara, A.; Vladimirescu, A.;


Year 2008


  1. A . Makosiej, P. Nasalski, B. Giraud, A. Vladimirescu and A. Amara, A Comparative Study of Innovative, sub-32nm SRAM, Insensitive to Process Variations and Transistor Mismatch, Current and Voltage Sense Amplifiers in Double-Gate CMOS, Proc. IEEE SOI Conference, Mohonk Mountain, New York, Oct. 2008
  2. P. Nasalski, A. Makosiej, B. Giraud, A. Vladimirescu and A. Amara, An Innovative sub-32nm SRAM Voltage Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch, Proc. IEEE Intl. Conference on Electronics, Circuits and Systems, Malta, Sep. 2008. Makosiej, P. Nasalski, B. Giraud, A. Vladimirescu and A. Amara,
  3. An Innovative sub-32nm SRAM Current Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch, ICICDT 2008, Grenoble, France.
  4. Adam Makosiej, Piotr Nasalski, Bastien Giraud, Andrei Vladimirescu and Amara Amara - An Innovative sub-32nm SRAM Current Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch - ICICDT, Grenoble, France, June 2008.
  5. Bastien Giraud, Amara Amara "Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS" IEEE Delta 2008, January 23-25 2008, Hong Kong
  6. 3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM P. Batude,. M.-A. Jaud, O. Thomas, L. Clavelier, A. Pouydebasque, M. Vinet, S. Deleonibus, A. Amara, IEEE International Conference on Integrated Circuit Design, pp81 (2008)
  7. An innovative ultra low voltage sub-32nm SRAM voltage sense amplifier in DG-SOI technology, 51st Midwest Symposium on Circuits and Systems, 2008. MWSCAS 2008. Pranav, P.; Giraud, B.; Amara, A.;

Year 2007

  1. Bastien Giraud, Andrei Vladimirescu and Amara Amara - A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation - ISCAS 2007, New Orleans
  2. Bastien Giraud, Andrei Vladimirescu and Amara Amara, In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS», ICICDT 2007, Austin USA.
  3. Bastien Giraud, Andrei Vladimirescu and Amara Amara, In-depth Analysis of 4T SRAM Cells in Double-Gate CMOS», ICICDT 2007, Austin USA
  4. A. Jalabert. Clermidy, F., Amara A., A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. 2 Jul 2007;

Year 2006

  1. T. Chawla, A. Amara and A. Vladimirescu, Yield, Power and Performance Optimization for Low-Power Clock Network under Parametric Variations in Nanometer-Scale Design, Proc. MWCAS06, Puerto Rico, Aug. 2006
  2. S. Léomant, A. Turier, L. Ben Ammar, A. Amara, "SRAM Dedicated PCMs For Leakage Characterization In Nanometer CMOS Technologies " IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, (IEEE DTIS06).
  3. T. Ea, F. Amiel, A. Michalowska, F. Rossant, A. Amara, "Contribution of Custom Instructions on SoPC for iris recognition application » IEEE ICECS 06, Dec.2006, Nice, France
  4. A.Jalabert, F.Clermidy, A.AMARA, "A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors", IEEE ICECS 06, Dec.2006, Nice, France
  5. A.Jalabert, F.Clermidy, A.AMARA, "A generic modeling approach for molecule-gated nanowire transistors", IEEE PRIME 11-16 June 2006, Otranto Italy
  6. S.Léomant, A.Turier,L.Benammara, A.Amara:"SRAM dedicated PCMs for Leakage Characterization in Nanometer CMOS Technologies", IEEE DTIS, September 05-07 2006 Tunis, Tunisia
  7. Nicolas L'Hostis, Olivier Thomas, Sebastien Haendler, Philippe Flatresse, Amara Amara, Marc Belleville "A Low Power dedicated 130nm PD-SOI technology: standby leakage reduction characterization", ICICDT 2006, Padova Italy
  8. T. Ea, F. Amiel, A. Michalowska, F. Rossant, A. Amara, « Erosion and dilatation implementation for Iris recognition system using different techniques on SoPC », DCIS 06, Nov.2006, Barcelona, Spain
  9. Contribution of Custom Instructions on SoPC for iris recognition application, Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara, ICECS 06, Dec.2006, Nice, France
  10. Erosion and dilatation implementation for Iris recognition system using different techniques on SoPC, Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara, DCIS 06, Nov.2006, Barcelona, Spain
  11. Contribution of Custom Instructions on SoPC for iris recognition application Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara ICECS2006 Nice december 2006

Year 2005

  1. O. Thomas, A. Vladimirescu and A. Amara, Ultra-Low-Voltage Current-Sense Read Circuits for CMOS SOI SRAMs, Proc. IEEE SOI Conf., Honolulu, Hawaii, Oct. 2005
  2. T. Ea, A. Valentian, F. Amiel, F. Rossant, A. Amara, Implementation on SoPC of algorithms dedicated to iris identification, Conference On Design of Circuits and Integrated Systems (DCIS), November 2005, Lisboa, Portugal
  3. O. Thomas, A. Vladimirescu and A. Amara, "Ultra-Low-Voltage Current-Sense Read Circuits for CMOS SOI SRAMs, Proc. IEEE SOI Conf., Honolulu, Hawaii, Oct. 2005
  4. F. Rossant, M. Torres Eslava, T. Ea, F. Amiel, A. Amara, "Iris identification and robustness evaluation of a wavelet packets based algorithm", International Conference on Image Processing (ICIP) September 2005.
  5. T. Ea, A. Valentian, F. Rossant, F. Amiel, A. Amara, "Algorithm implementation for iris identification", IEEE 48th Midwest Symposium on Circuits and Systems (MWSCAS) August 2005, Cincinnati, Ohio, USA
  6. Alexandre Valentian, Amara Amara, Nicolas l'Hostis, Philippe Flattresse,, "A 130nm Partially Depleted SOI Technology Menu for Low-Power Applications", IEEE NEWCAS June 19-23 2005, Quebec, Canada
  7. Olivier Thomas, Amara Amara, "Ultra Low Voltage Design Considerations of SOI SRAM Memory Cells", ISCAS May 23-26 2005, Kobe Japan
  8. Amara Amara, Alexandre Valentian, "SOI Partially -Depleted Ultra Low Voltage SRAM and Digital Circuit Design", ICICDT May 10-11 2005, Austin Texas
  9. Thomas Ea, Alexandre Valentian, Frédéric Amiel, Florence Rossant, Amara Amara - Implementation on SoPC of algorithms dedicated to iris identification - DCIS'05, November 2005, Lisboa, Portugal
  10. Iris identification and robustness evaluation of a wavelet packets based algorithm, F.Rossant, M.Torres Eslava, T.Ea, F.Amiel, A.Amara, ICIP'05, September 2005, Genoa, Italy, ISBN 0-7803-9135-7
  11. Thomas Ea, Alexandre Valentian, Florence Rossant, Frédéric Amiel, Amara Amara, Algorithm implementation for iris identification, MWSCAS'05, August 2005, Cincinnati, Ohio, USA
  12. Amara Amara, Frédéric Amiel, Thomas Ea FPGA vs. ASIC For Low Power Applications FTFC'05, Mai 2005, Paris
  13. Thomas Ea, Alexandre Valentian, Florence, Rossant, Frédéric Amiel, Amara Amara, Algorithm implementation for iris identification, MWSCAS'05 August 2005, Cincinnati, Ohio
  14. T. Ea, A. Valentian, F. Amiel, F. Rossant, A. Amara - Implementation on SoPC of algorithms dedicated to iris identification - DCIS'05, November 2005, Lisboa,Portugal
  15. F. Rossant, T. Ea, F. Amiel, M. Torres Eslava, A.Amara - Identification par analyse en paquets d'ondelettes de l'iris et tests de robustesse - Gretsi05 Sept 2005 Louvain La Neuve

Tutorials, keynotes, panels and invited talks in Conferences and workshops

  1. SRAM Memory Design with Double-Gate Transistors ICONAME Workshop, India Jan. 2008, Keynote
  2. Panel organizer and moderator at IEEE NEWCAS 2005, Montreal, Quebec, Canada
  3. Panel organizer and moderator at IEEE ICICDT 2007, Austin, Texas, USA
  4. Panel organizer and moderator at SAME 2006, Sophia Antipolis, Nice 2006, France,
  5. New Devices and Structures: Molecular Electronics and Double Gate, National Workshop on Challenges in VLSI, India Dec. 2006, invited talk
  6. Panelist in a rump up session, ICICDT 2005, Austin, USA
  7. Panelist in a rump up session 2009 International Symposium on Digital Life Technologies (ISDLT), : Human-Centric Smart Living Technology 2009, Taiwan
  8. Power-Aware Design Techniques NEWCAS 2005, Canada June 2005, Tutorial
  9. VHDL for Low Power NEWCAS, Canada June 2004, invited talk
  10. SOI for Ultra Low Voltage Applications NEWCAS, Canada June 2004, Tutorial
  11. VHDL for Low Power Marlow Workshop, Switzerland Mar. 2004, invited talk
  12. Low Power Design for portable applications ACM'02, Algeria Oct. 2002, Keynote

Invited lectures, invited talks in industry and academia

  1. Is there a room for Post-CMOS technologies in Low Power Applications?ASTAR IME, Singapore,August 2010,
  2. Designing Beyond the CMOS Era Pondicherry Electrical Engineering, India June 2007, invited talk
  3. Low Power design techniques Louvain-La-Neuve University, Belgium Dec. 01, Nov 02, Dec. 2003 to 2010, lectures43
  4. Design and Technology Interaction EPFL, Switzerlnd May 2006, invited talk
  5. RTL Level Power Optimization Techniques UC Dublin, Ireland 2005, lecture
  6. Low Power Design techniques for Portable Devices SIIT Bangkok Thailand July 2005, 2-weeks lecture
  7. Low Power design techniques (lecture) CEA/LETI, France 2005, 2007, lecture
  8. VHDL for Low Power Texas Instruments, India May 2004, invited talk
  9. Ultra Low Voltage SOI Circuits IIT Chennai, India 2004, invited talk
  10. Ultra Low Voltage SOI Circuits Kolkata Univ., India 2004, invited talk
  11. Ultra Low Voltage SOI Circuits DA-IICT, India 2004, invited talk
  12. Low Voltage Circuit Design U C Davis, USA Feb. 2002, invited talk
  13. Low Power and Low Voltage circuits design Infineon, Germany 2001, invited talk Invited Talk

 

 

     
E-mail : amara.amara@isep.fr